Semiconductor device designers often desire to increase the level of integration or density of features within a semiconductor device by reducing the dimensions of the individual features and by reducing the separation distance between neighboring features. In addition, semiconductor device designers often desire to design architectures that are not only compact, but offer performance advantages, as well as simplified designs.
A relatively common semiconductor device is a memory device. A memory device may include a memory array having a number of memory cells arranged in a grid pattern. One type of memory cell is a dynamic random access memory (DRAM). In the simplest design configuration, a DRAM cell includes one access device, such as a transistor, and one storage device, such as a capacitor. Modern applications for memory devices can utilize vast numbers of DRAM unit cells, arranged in an array of rows and columns. The DRAM cells are electrically accessible through digit lines and word lines arranged along the rows and columns of the array.
Reducing the dimensions and spacing of memory device features places ever increasing demands on the methods used to form the memory device features. For example, one of the limiting factors in the continued shrinking of memory devices is the resistance of the contacts associated therewith. As used herein, a “contact” refers to a connection facilitating a conductive pathway between at least two structures. For example, in a DRAM device exhibiting a dual bit memory cell structure, a digit line contact is provided between a digit line and an access device (e.g., a transistor) formed in or above a substrate, and storage node contacts are formed between the access device and a storage node (e.g., a capacitor) where electrical charge may be stored. As the dimensions of memory device (e.g., DRAM device) features decrease, the dimensions of the contacts associated therewith also decrease, resulting in increased contact resistance. Increased contact resistance decreases the drive current of the memory device, which can adversely affect memory device performance.
One approach toward decreasing contact resistance within a memory device has been to increase the surface area of the contacts thereof. For example, material may be removed from multiple surfaces of a memory device feature to form a three-dimensional (3D) contact exhibiting greater contact surface area than the memory device feature would otherwise exhibit. However, conventional methods of forming 3D contacts for a DRAM device structure exhibiting lower critical dimensions, such as critical dimensions less than about 20 nanometers (nm), can require complex and costly processes to sufficiently form and align 3D storage node contacts relative to digit line (e.g., bit line) contacts to ensure proper performance of the DRAM device.
For example, one conventional method of forming 3D contacts exhibiting lower critical dimensions includes transferring a pattern of openings and features in a mask structure into a hard mask material overlying a semiconductive material, and then using the patterned hard mask material to selectively etch (e.g., selectively dry etch) the underlying semiconductive material and form semiconductive pillars each including two storage node (e.g., memory element) contact regions and a digit line contact region laterally between the two storage node contact regions. However, transferring the pattern of the mask structure into the hard mask material typically requires aspect ratio dependent etching (ARDE) of the hard mask material, which can effectuate undesirable structural characteristics in the subsequently formed semiconductive pillars. During ARDE, the rate of material (e.g., hard mask material) removal depends on the aspect ratio of the opening (e.g., trench) being formed, which is defined as the ratio of the depth of the opening to the width (e.g., diameter). Openings with relatively higher aspect ratios are etched more slowly than openings with relatively smaller aspect ratios. In other words, the etch rate, in terms of linear depth etched per unit time, is smaller for high aspect ratio openings than for low aspect ratio openings. As a result, some features (e.g., pillar structures) of the patterned hard mask material can exhibit variable lateral dimensions across the heights thereof depending on variations in the widths of the openings in the mask structure. In turn, such variable lateral dimensions can effectuate undesirable lateral dimensions and shapes in the semiconductive pillars formed using the patterned hard mask material that can leave very little process margin to circumvent digit line to storage element (e.g., memory element) shorts in a DRAM device including the semiconductive pillars.
A need, therefore, exists for new, simple, and cost-efficient methods of forming semiconductive device structures for a semiconductor device (e.g., a DRAM device), such as, for example, DRAM device structures having critical dimensions less than about 20 nm.